Manufacturing of semiconductor devices, in particular integrated circuits having multiple-layered structures with various metal and non-metal layers laminated on a semiconductor substrate, typically involves an application of several metal layers onto a substrate or onto other previously deposited layers.
These layers may have a complicated planar topology since these layers may constitute thousands of individual devices, which in combination form an integrated circuit or so-called “chip”. Modem chips may have metal or dielectric layers with thicknesses from tens of Angstroms to fractions of a micron.
It is understood that thin metallic films used in integrated circuits of semiconductor devices function as conductors of electric current. Furthermore, it is known that densities of signal currents in metallic interconnections used in integrated circuit may reach extremely high values that generate such phenomena as electromigration associated with spatial transfer of mass of conductor films. Therefore the characteristics and properties of the deposited metal films (uniformity of film thickness, low electrical resistivity, etc.) determine performance characteristics and quality of the integrated circuit and of the semiconductor device as a whole.
In view of the above, thin metal films used in integrated circuits should satisfy very strict technical requirements relating to metal deposition processes, as well as to repeatability and controllability of the aforementioned processes.
A wide range of metals is utilized in the microelectronic manufacturing industry for the formation of integrated circuits. These metals include, for example, nickel, tungsten, platinum, copper, cobalt, as well as alloys of electrically conductive compounds such as silicides, solders, etc. It is also known that coating films are applied onto substrates with the use of a variety of technological processes such chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, and electroless plating. Of these techniques, electroplating and electroless plating tend to be the most economical and most promising for improvement in characteristics of the deposited films. Therefore, electroplating and electroless plating techniques successfully replaces other technologies.
Electroplating and electroless plating can be used for the deposition of continuous metal layers as well as patterned metal layers. One of the process sequences used by the microelectronic manufacturing industry to deposit a metal onto semiconductor wafers is known to as “damascene” processing. In such processing, holes, commonly called “vias”, trenches and/or other recesses are formed on a workpiece and filled with a metal, such as copper. In the damascene process, the wafer, with vias and trenches etched in the dielectric material, is first provided with a metallic seed layer, which is used to conduct electrical current during a subsequent metal electroplating step. If a metal such as copper is used, the seed layer is disposed over a barrier layer material, such as Ti, TiN, etc. The seed layer is a very thin layer of metal, which can be applied using one or more of several processes. For example, the seed layer of metal can be laid down using physical vapor deposition or chemical vapor deposition processes to produce a layer with the thickness on the order of 1,000 Angstroms. The seed layer can advantageously be formed of copper, gold, nickel, palladium, or other metals. The seed layer is formed over a surface, which may contain vias, trenches, or other recessed device features.
A metal layer is then electroplated onto the seed layer in the form of a continuous layer. The continuous layer is plated to form an overlying layer, with the goal of providing a metal layer that fills the trenches and vias and extends a certain amount above these features. Such a continuous layer will typically have a thickness on the order of 5,000 to 15,000 Angstroms (0.5-1.5 microns).
After the continuous layer has been electroplated onto the semiconductor wafer, excess metal material present outside of the vias, trenches, or other recesses is removed. The metal is removed to provide a resulting pattern of metal layer in the semiconductor integrated circuit being formed. The excess plated material can be removed, for example, using chemical mechanical planarization. Chemical mechanical planarization is a processing step, which uses the combined action of chemical removal agents, or a chemical removal agents with an abrasive, which grinds and polishes the exposed metal surface to remove undesired parts of the metal layer applied in the electroplating step.
Disadvantages associated with electroplating are technical problems in connection with designing of reactors used in the electroplating of semiconductor wafers. Utilization of a limited number of discrete electrical contacts (e.g., 8 contacts) with the seed layer about the perimeter of the wafer ordinarily produces higher current densities near the contact points than at other portions of the wafer. This non-uniform distribution of current across the wafer, in turn, causes non-uniform deposition of the plated metallic material. Current thieving, affected by the provision of electrically conductive elements other than those, which contact the seed layer, can be employed near the wafer contacts to minimize such non-uniformity. But such thieving techniques add to the complexity of electroplating equipment, and increase maintenance requirements.
Another problem associated with electroplating of wafers concerns efforts to prevent the electric contacts themselves from being plated during the electroplating process. Any material plated to the electrical contacts must be removed to prevent changing contact performance. While it is possible to provide sealing mechanisms for discrete electrical contacts, such arrangements typically cover a significant area of the wafer surface, and can add complexity to the electrical contact design.
The specific metal to be electroplated can also complicate the electroplating process. For example, electroplating of certain metals typically requires use of a seed layer having a relatively high electrical resistance. As a consequence, use of the typical plurality of electrical wafer contacts (for example, eight discrete contacts) may not provide adequate uniformity of the plated metal layer on the wafer. Reduction in sizes of such features as vias and trenches also requires thinner layers having higher resistivity, which in turn may generate a high potential drop from the wafer edges to the central part, whereby the rate of deposition in the central area is significantly reduced.
Beyond the contact-related problems discussed above, there are also other problems associated with electroplating reactors. As device sizes decrease, the need for tighter control over the processing environment increases. This includes control over the contaminants that affect the electroplating process. The moving components of the reactor, which tend to generate such contaminants, should therefore be subject to strict isolation requirements.
Still further, existing electroplating reactors are often difficult to maintain and/or reconfigure for different electroplating processes. Such difficulties must be overcome if an electroplating reactor design is to be accepted for large-scale manufacturing.
One drawback associated with copper deposition by electroplating is the fact that for very small features on microelectronic workpieces (sub 0.1 micron features), copper deposition by electroplating can lack conformity with the side walls of high aspect ratio vias and trenches, and can produce voids in the formed interconnects and plugs (vias). This is often due to the non-conformity of the copper seed layer deposited by PVD or CVD. As a result, the seed layer may not be thick enough to carry the current to the bottom of high aspect ratio features.
An alternate process for depositing copper onto a microelectronic workpiece is known as “electroless” plating which is the deposition of metals on a catalytic surface from a solution without an external source of current. For example, this process can be used as a preliminary step in preparing plastic articles for conventional electroplating. After cleaning and etching, the plastic surface is immersed in solutions that react to precipitate a catalytic metal in situ, palladium, for example. First the plastic is placed in an acidic stannous chloride solution, then into a solution of palladium chloride; palladium is reduced to its catalytic metallic state by the tin. Another way of producing a catalytic surface is to immerse the plastic article in a colloidal solution of palladium followed by immersion in an accelerator solution. The plastic article thus treated can now be plated with nickel or copper by the electroless method, which forms a conductive surface, which then can be plated with other metals by the conventional electroplating method.
Along with the electroplating method, the electroless method also has found wide application in the manufacture of semiconductor devices.
As compared to electroplating, electroless plating is a selective process, which can be realized with very thin seeds or without the use of seeds at all. Since an electroless process is not associated with the use of an electric current source, electroless plating results in more uniform coatings in view of the absence of discrete contacts. Electroless plating can be realized with the use of simple and inexpensive equipment and with a high aspect ratio gap fill.
Given below are several examples of methods and apparatuses for electroless plating, specifically for use in the manufacture of semiconductor devices.
U.S. Pat. No. 5,500,315 issued in 1996 to J. Calvert, et al. discloses an electroless metal plating-catalyst system that overcomes many of the limitations of prior systems. In one aspect of the invention, a process is provided comprising steps of providing a substrate comprising one or more chemical groups capable of ligating to an electroless plating catalyst, at least a portion of the chemical groups being chemically bonded to the substrate; contacting the substrate with the electroless metal plating catalyst; and contacting the substrate with an electroless metal plating solution to form a metal deposit on the substrate. The chemical groups can be, for example, covalently bonded to the substrate. In another preferred aspect, the invention provides a process for selective electroless metallization, comprising steps of selectively modifying the reactivity of a substrate to an electroless metallization catalyst; contacting the substrate with the electroless metallization catalyst; and contacting the substrate with an electroless metallization solution to form a selective electroless deposit on the substrate. The substrate reactivity can be modified by selective treatment of catalyst ligating groups or precursors thereof on the substrate, for example by isomerization, photocleavage or other transformation of the ligating or precursor groups. Such-direct modification enables selective plating in a much more direct and convenient manner than prior selective plating techniques. Specifically, the aforementioned patent provides selective electroless plating without the use of a photoresist or an adsorption type tin-containing plating catalyst.
The method described in the above patent includes an electroless catalyst system that requires fewer and simpler processing steps in comparison to current Pd/Sn colloid catalyst adsorption based systems; use of more stable and convenient catalysts, including tin-free catalysts; and improved catalyst adhesion to a substrate allowing plating of more dense initiation and of greater uniformity and selectivity. The invention also provides selective patterning of substrate ligating groups, thereby enabling a selective metal deposit without the use of a conventional photoresist patterning sequence.
U.S. Pat. No. 6,309,524 granted to D. Woodruff, et al. in 2001 discloses a universal electroplating/electroless reactor for plating a metal onto surfaces of workpieces. An integrated tool for plating a workpiece comprises a first processing chamber for plating the workpiece using an electroless plating process and a second processing chamber for plating the workpiece using an electroplating process. A robotic transfer mechanism is used that is programmed to transfer a workpiece to the first processing chamber for electroless plating thereof and, in a subsequent operation, to transfer the workpiece to the second processing chamber for electroplating thereof.
It should be noted that a common problem in using bathes, which is especially true for the electroless deposition process, is that foreign particles or contaminants will be deposited on the substrate surface of the wafer when transferring the wafers from one bath to another bath. Another common problem is the exposure of the substrate surface of the wafer to air during the transfer (from bath to bath) can cause the non-wetting of deep and narrow trenches in the surface or small (contact) holes in the surface because of electrolyte evaporation. And yet another common problem is that exposure to air may cause oxidation of the catalytic surface that will result in poor catalytic activity and poor quality metal deposits. This problem becomes especially troublesome when using materials that easily oxidize in air such as copper. To produce high quality metal deposits in the submicron range, therefore, it is more desirable not to transfer the wafer between the process chambers and to avoid exposing the wafer to air by using a single bath or process chamber and moving the different fluids for each step in the process through the process chamber.
The above problems are solved by the system described in U.S. Pat. No. 5,830,805 issued in 1998 to Y. Shacham-Diamand, et al. This patent discloses an electroless deposition apparatus and method of performing electroless deposition for processing a semiconductor wafer that uses a closed process chamber to subject the wafer to more than one processing fluid while retaining the wafer within the chamber. The invention is useful for manufacturing processes that include depositing, etching, cleaning, rinsing, and/or drying. The process chamber used in the preferred embodiment of the apparatus of the above patent is an enclosed container capable of holding one or more semiconductor wafers. A distribution system introduces a first fluid into the chamber for processing the wafer and then removes the first fluid from the chamber after processing the wafer. The distribution system then introduces the next fluid into the chamber for processing the wafer and then removes the next fluid from the chamber after processing the wafer. This procedure continues until the manufacturing process finishes. The fluids used in the present invention depends on the process performed and may include fluids such as DI water, N2 for flushing, and electrolytic solutions comprising reducing agents, complexing agents, or pH adjusters.
The fluid enters the sealed process chamber through an inlet, and exits the chamber through an outlet. As the fluid enters the process chamber, the fluid is dispersed across the wafer in a uniform flow. A recirculation system moves the fluid through the process chamber using a temperature control system, chemical concentration monitoring system, pump system, and a filtration system before recirculating the fluid back through the process chamber.
Additional embodiments include: a rotatingly mounted tubular wafer housing with a wafer mounted on either or both sides of the housing surface; an inner core mounted inside of the tubular housing when mounting a wafer on the inside surface of the housing; and a dispersal apparatus for dispersing the fluid in a uniform flow over the wafer. The processing chamber can be provided with a heater and a temperature control system.
In spite of their advantages, the known electroless processes have temperature of the working chemical solution as one of the main parameters. It is known that speed of deposition in an electroless process depends on the temperature in a degree close to exponential. For example in an article published in Electroless Nickel Plating, Finishing Publications Ltd., 1991, W. Riedel states (page 39 of the article) that temperature is the most important of parameters affecting the deposition rate and that for a Ni-P electroless process the deposition rate increases twofold for every 10 degrees of bath temperature.
Furthermore, for the metal interconnects on the surface of the wafer one of the major requirements is low resistivity. Copper was chosen as the close second best for fulfilling this requirement. However, due to the presence of various additives in the interface between the PVD Cu seeds and ECD (electroplating copper deposition) Cu, resistivity is disproportionally increased as compared to much thinner electroless-deposited Cu layer. This phenomenon was reported by S. Lopatin at AMC, 2001.
It has been also shown by Y. Lantasov, et al. in “Microelectronics Engineering”, No. 50 (2000), pp. 441-447, FIG. 2, that resistivity of ELD Cu strongly depends on deposition conditions, and that at higher temperatures it is possible to obtain a material with low resistivity.
However, it is understood that electroless plating at high temperatures leads to significant non-uniformities in the deposited layers. This occurs due to local temperature fluctuations. The higher the temperature, the greater such fluctuations. Stabilization of elevated temperatures in large volumes of the solution tanks is associated with the use of complicated temperature control systems and temperature maintaining systems (seals, thermal insulations, etc.). This, in turn, increases the cost of the equipment and maintenance.
For the reasons described above, manufacturers of semiconductor equipment prefer to use electroless processes carried out at room temperature. Low speeds of deposition are compensated by utilizing a multiple-station deposition equipment with simultaneous operation of a number of substrates in a number of chambers arranged in series. Such equipment requires a large production space and dictates the use of large volumes of the solutions. Furthermore, an additional space is needed for the preparation, storage, and post-use treatment of the solutions. This, in turn, creates environmental problems.
Another common drawback of existing electroless deposition apparatuses is low speed of deposition, which in general depends on the type of the deposited material and even in the best case does not exceed 100 nm/min, but normally is much lower. For example, for CoWP the speed of deposition can be within the range from 5 nm/min to 10 nm/min.